DRAM technology builds redundancy into DRAM arrays. Such redundancy allows for reassigning data storage to another redundant row/column/block of a memory array to compensate for inevitable defects in processing. Since modern DRAM arrays are so vastly large in number of cells, and so vastly small in terms of actual size per cell, even small errors in processing can affect cells. By building redundancy into DRAM arrays, yield is improved since reprogramming of some portion of a DRAM array is far superior to wasting the entire part due to a few small defects. Since the defect rate is actually not very large, a single redundancy array is sufficient to compensate for most errors in processing of a modern DRAM array.
In redundancy in DRAM arrays, spare elements such as rows or columns are used as logical substitutes for a defective element or elements. The substitution of redundant rows or columns for defective rows or columns is controlled by a physical encoding scheme. As memory density and size increase, redundancy becomes more and more important. Row and column redundancy are commonplace in modern DRAMs. Further, some DRAM manufacturers have begun to experiment with entire subarray redundancy.
Row redundancy replaces bad word lines with good word lines. Any number of problems could exist on word lines, including shorted or open word lines, word line to digit line shorts, bad transistors or storage capacitors, and the like.
A ROM embedded DRAM is a DRAM array that has been modified slightly to allow for a portion of the DRAM array cells to be converted into ROM cells. Such a ROM embedded DRAM is described in greater detail in U.S. Pat. No. 6,134,137 issued Oct. 17, 2000 entitled “ROM-Embedded-DRAM”, incorporated herein by reference. U.S. Pat. No. 6,134,137 teaches that slight modifications in fabrication masks allow DRAM cells to be hard programmed to Vcc or Vss by shorting the cell to word lines. The memory reads the ROM cells in a manner that is identical to reading the DRAM cells.
In a ROM embedded DRAM, problems with DRAM cells that have been converted to ROM cells can contribute to ROM defects. For example, if a DRAM cell on a portion of the ROM embedded DRAM is to be programmed by hard shorting to a 0 logic, but it is open and stuck at a 1 logic, there would be an error.
In row redundancy, when a row address is strobed into a DRAM, the address is compared to a known bad address bank. If a bad address is requested, a replacement word line is fired in place of the defective or bad word line. The replacement word line can appear anywhere on the DRAM array. Repair of rows is termed either global or local. If the replacement word line is in the same subarray as the bad word line, the repair is termed a local repair. If the bad word line is in a different subarray than the replacement word line, the repair is termed a global repair. Global repair is more desirable because the amount of repair is limited in each subarray. If one particular subarray has a large number of defects, and all the repairs are local, the subarray could run out of available replacement rows, and the entire chip becomes scrap. Global repair is very effective for cluster type failures, and is especially helpful for larger DRAMs.
There are many different redundancy repair schemes, which are beyond the scope of this application, but which are readily known to those of skill in the art. For example only and not by way of limitation, repair schemes include antifuses, dynamic logic, and the like. Redundant word lines are often capable of pretesting to determine whether they are good or bad before actual selection of the replacement word line. This allows for selection of a good replacement word line and the concordant lack of necessity to change many replacement word lines to second replacement word lines.
Column redundancy schemes are also available on most modern DRAMs. Column redundancy differs from row redundancy in that it is often the case that column addresses can be accessed multiple times per row address strobe cycle. Each column is held open until a subsequent column appears. Typical column fuse blocks for column redundancy are built using static logic gates rather than dynamic logic gates. Dynamic gates require a precharge and evaluation (P&E) and sufficient time to perform the P&E may not be present with unpredictable column addressing. In some modern DRAMs, such P&E will work, and in that case, the schemes for column redundancy are very close to that of row redundancy. However, in some other DRAM architectures, static redundancy is used.
It would be desirable to implement redundancy in the ROM portion of a ROM embedded DRAM.